SD Express IP Core

SD Express FPGA IP core enables high-speed data transfer by leveraging PCIe and NVMe protocols over an SD card interface. It supports backward compatibility with legacy SD modes while offering significantly enhanced performance for storage applications. This enables the high-speed data transfer for next-generation storage applications as it supports the data rates significantly higher than traditional SD cards. Designed for FPGA-based implementations, it provides flexibility for custom storage solutions in embedded and industrial applications.

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Design Support

Features	Details
SD Mode Features	Compliant with SD Host Controller Standard Specification Version 3.0 Compliant with SD Physical Layer Specification Version 3.0 Supports 1-bit,4-bit SD modes Supports SD Card Detection input pin Supports SD Card Write Protection input pin Supports programmable clock frequency generation to the SD card Supports Interrupt and ADMA2 transfer mode of operation Individual 2Kbyte data buffer for read and write Cyclic Redundancy Check (CRC) for command and data Supports timeout monitoring for response, data, CRC token & busy Supports a maximum block length of 2Kbyte Supports both single block and multi block data transfer Supports 32-bit AXI4 memory mapped interface towards host processor Supports 32-bit AXI4 lite interface towards SD host Controller **Support Default speed and High-Speed including SDR12, SDR25, DDR50, SDR50 andSDR104 modes
PCIe Mode Features	PCIe Express (PCIe) Gen 3 or Gen 4; 1 or 2 lanes* NVM-Express revision 1.3 or later supported over PCIe interface Dual simplex point to point connection Identifies the card as standard Mass storage controller – NVMe device Supports the legacy SD UHS-1 interface for backward compatibility Supports AXI4 stream interface towards host processor Supports AXI4 lite interface towards PCIe root port IP Supports SDR50 and SDR104 mode. Please contact us to check the SDR50 and SDR104 mode support in target device *** Support PCIe Gen3 or Gen4 depends on the target device
Highlights	Complaint with SD Physical Layer Specification Version 9.1 Support for SD express as well as well as legacy SD mode Integrates the iWave NMVe host controller with legacy SD controller for non-soc FPGA implementation Uses the NVMe part of Linux with legacy SD controller for SOC FPGA implementation Software support includes the standard SD driver for Linux and simplified baremetal driver