Agilex^TM 7 F-Series SmartNIC – 200G

G51-AFibre-200G®

3/4 Length PCIe Gen4 x16 Host Interface
Dual Front Panel QSFP-DD/QSFP28 Cages (200GbE)
Single Gen4 x4 M.2 NVMe Slot
Data Plane Development Kit (DPDK)
Datacentre Applications

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Features	Details
PCIe NIC Card	218mm x 115.15mm, 3/4 Length, Full Height, Dual Slot with Active Cooling PCIe Card. PCIe Gen4 x16 Host Interface Front Panel QSFP-DD Cage (200GbE/100GbE) Single Gen4 x4 M.2 NVMe Slot 2 DDR4 Channels HPS – Single 8GB, 72b, 3200MHz at 409.6 Gbps FPGA – Single 8GB, 72b, 3200MHz at 409.6 Gbps Single Gen4 x4 OCU Link Connector
OFS FIM	Line rates with F-Tile Ethernet: 200G – 8 x 25G 100G – 4 x 25G PCIe: F-tile PCIe Gen4x16 PCI Capabilities: SR-IOV, ACS, Data Link Hard Processor System (HPS) with 8GB DDR4, x72 (with ECC), 3200 MHz, 8GB with a max throughput of 409.6 Gbps. Virtualization: 5 physical functions/3 virtual functions with ability to expand. Memory: Single Fabric DDR4 channels, x72 (with ECC), 3200 MHz, 8GB with a max throughput of 409.6 Gbps. For more information on Intel OFS refer the following Link – https://ofs.github.io/ofs-2024.2-1/
Host Server Environments for OFS	PCIe Gen 4×16 Disk: Free Space upto 50GB Memory: 128GB BIOS: Enable IOMMU, Huge pages, PCI Reallocation, Disable PCI-ASM. Supported OS: Ubuntu 22.04, RedHat 8 Supported Libraries & Applications: OPAE SDK, HE-Exerciser, LinuxPTP, DPDK
OFS Software	HE-Exerciser The host interacts with the FPGA using the Linux DFL and OPAE libraries https://ofs.github.io/ofs-2024.2-1/sw/fpga_api/prog_guide/FPGA-lib-1.png HE applications communicate with the HSSI, Loopback, Traffic Generator, and Memory modules within the AFU region of the FPGA. The application also extends its functionality to transmit workloads over QSFP ports at various speeds. DPDK-IFPGA The DPDK based IFPGA libraries help to interact with Management modules. The IFPGA Rawdev Driver utilizes Intel FPGA Software Stack OPAE (Open Programmable Acceleration Engine) for FPGA management. Management Modules include FPGA status check, FPGA reset or reboot, PR reset, Read/Write PCI configuration space, bind or unbind FPGA with kernel drivers. Linux PTP The kernel exposes ToD IP as a PTP Hardware Clock to the Linux PTP stack, allowing the system clock to synchronize with the ToD information The phc2sys utility to access ToD information and synchronize the system clock.

Application Stack Accelerator Function (ASAF):

VirtIO-net emulated PCIe devices
Management Tool for network data path configuration
Status or statistics retrieval from Ethernet

DYNANIC:

Uses NDK (Network Development Kit) Architecture
Contains Network module to handle Ethernet packet transmission and reception
Optimized for 200Gbps high throughput
A user-dedicated space in NDK firmware for application

Open FPGA Stack (OFS):

A Framework for custom workloads
Manage and access programmable accelerators using OPAE Tool
AFU accelerates functions on an OPAE hardware platform
Dynamically reconfigure FPGA parts using Partial Reconfiguration
More Info: https://ofs.github.io/ofs-2024.2-1/

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