January 20, 2026
Article
MIL‑STD‑1553 is a dual-redundant serial data bus standard widely used for avionics, aerospace, defence and space systems. Originally standardized in the 1970s, it defines how a Bus Controller (BC), multiple Remote Terminals (RT), and optionally a Monitor Terminal (MT) communicate on a shared bus at ~1 Mbps. The standard ensures robust, deterministic, redundant communication essential in safety or mission-critical systems such as aircraft subsystems, satellites, weapon systems, etc. Over decades, implementations moved from discrete transceivers + protocol logic, through ASICs / mixed-signal ICs, to modern implementations using FPGA IP cores.
Especially in the context of modern embedded systems / FPGA-based designs, a 1553B IP core brings several advantages many of which have been recognized industry-wide.
iWave’s MIL-STD-1553B IP core represents a modern, flexible, efficient, and cost-effective way to implement the trusted MIL-STD-1553B bus standard — leveraging FPGA logic instead of fixed ICs. For companies like iWave Global with FPGA/IP-core expertise and FPGA-based SoMs or ODM ambitions, this approach offers the ability to integrate legacy-standard bus capability into advanced, custom hardware — saving board space, reducing BOM, improving flexibility, and lowering risk of obsolescence.
In addition, iWave supports customers by providing the necessary certification artifacts required for DO-254 compliance. This significantly simplifies the certification process and reduces development risk for safety-critical programs. By offering both the IP core and the associated compliance deliverables, iWave ensures a complete and streamlined solution which enables customers to focus on system integration and deployment with confidence.
For more information, please visit www.iwave-global.com or reach out to us at mktg@iwave-global.com
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