RoCEv2 IP Core

Name: 100G RoCEv2 IP
Brand: iWave Global
Availability: InStock

The RoCEv2 IP Core delivers RDMA over Converged Ethernet (RoCEv2) functionality, compatible with standard Ethernet MAC interfaces. It enables low latency, high throughput, zero-copy, and kernel-bypass data transfers, ensuring efficient performance. The IP core supports RDMA SEND, WRITE, and READ operations, along with iCRC-based integrity checks for reliable communication.

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White Paper

High-Speed Ethernet on FPGA & SmartNIC

Features

Details

RoCEv2

Compliant with RoCEv2 specification and RNIC products
Hardware operated Reliable connection (RC) service
Easy integration with 10G, 25G, 40/50G, 100G, 200G and 400G Ethernet MAC
Supports RDMA SEND, RDMA RECEIVE, RDMA READ and RDMA WRITE operations
Configurable Queue Pair support and QP1 Support for Connection Management
Retransmission logic implemented in hardware
Configurable retransmission buffer size depends on the resource availability
Memory Protection domain implemented in FPGA
Supports AXI4 Lite Interface for control and status register access
Supports either AXI MM interface for data transfer using built in DMA or AXI Stream interface for direct data streaming without DMA
Supports RoCEv2 packets and supports ARP and ICMP packets though sideband interface
Support for L2 (Ethernet) / L3 (IP) RoCE v2 path modes and IP Layer (L3) support IPV4
Ethernet MTU is configurable up to 9000 bytes and RoCE MTU supports up to 4096 bytes
VLAN (PCP) / IP (DSCP) marking are not supported
Advanced features like PFC/ECN/DCQCN are not supported
Uses vendor provide Ethernet MAC IP for MAC implementation

Highlights

RoCEv2 IP core provides RDMA over Converged Ethernet implementation in FPGA. RoCEv2 IP core provides Low latency, High throughput and is compatible with standard MAC interface

ZU11/17/19 Dev Kit

iWave 100G RoCEV2 IP core has been tested on AMD/Xilinx Zynq MPSoC FPGAs using iWave’s ZU11/17/19 based development kit. The QSFP connector on the carrier card provides a 100G Ethernet interface, enabling communication either with a host system supporting 100G RoCEV2 or with another development kit for IP evaluation.
Integration Manual