Documents
Documents
Design Support
Software
| Features | Details |
|---|---|
|
SoC |
Agilex 7 (R24C) SoC FPGA Compatible Agilex 7 R24C Package Family
Field Programmable Gate Array (FPGA)
Hard Processing System (HPS)
|
| Memory & Storage | 8GB DDR4 with ECC for HPS (64bit + 8bit) 8GB DDR4 with ECC for FPGA (64bit + 8bit) 2 x 144Mb QDR-IV For FPGA (18bit) 32GB eMMC (Expandable up to 128GB) 1Gb QSPI Flash (Expandable up to 2Gb) EEPROM |
| 3U-VPX Front Panel Features | USB 2.0 through USB Type-C Connector Debug UART through 3-Pin Header 1G Ethernet through 9-Pin Header |
| Board Management Controller | VITA 46.11-2022 compliant with full Tier-3 support. MCU for System Management Temperature Sensor Time Elapse Counter EEPROM Voltage monitoring and control |
| Clock Generators | Clock Synthesizer with 10 Outputs 3 LVDS Clock Buffers for Transceivers reference Clocks |
| Other | Slot Profile: SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n Module Profile: MOD3-PAY-1F1U1S1S1U1U4F1J -16.6.13-n SOSA-aligned 3U-VPX Backplane Features |
| 3U-VPX Connector (P0+P1A)3U-VPX Connector (P0+P1A) | DP01[3:0] – 40GBASE-KR4 DPutp01 – 10GBASE-KR CPutp01 – 10GBASE-KR 1 REF Clock Differential Pair Input 1 AUX Clock Differential Pair Input I2C x 2 JTAG UART x 1 Control Signals 3V3_AUX Power Input 12V Power Input |
| 3U VPX Backplane: Connector – P2A |
Expansion Plane Port
|
| 3U-VPX Connector (P1B+P2A) | EP00-EP07 – PCIe Gen3 x8 EP08-EP15 – PCIe Gen3 x8 UART x 1 |
| Hybrid Connector (P2B) | SDI IN x 4 (Through coaxial connectors) SDI Out x 4 (Through coaxial connectors) 8 Fiber Optical Transceiver (4 x 2) Upto 28.125Gbps (Through two Firefly connectors) |
| Form Factor | 160mm X 100mm (3U-VPX Standard) |
| Power | 12V through 7 Power Pins of P0A 3V3_AUX through 1 Power Pins of P0A |
| Compliance | REACH & RoHS3 Compliant |

For any highly integrated FPGA VPX Plug-in Module, thermal design is a very important factor. iWave supports a VITA 65.0 compliant 3U Conduction Cooled Heat Spreader.



