Zynq™ Ultrascale+™ SmartNIC – 100G

G35-XFibre-100G®

3/4 Length PCIe Gen3 x16 Host Interface
Dual Front Panel QSFP-DD/QSFP28 Cages (2 x 100GbE)
FPGA and Quad Arm Cortex-A53
Data Plane Development Kit (DPDK)
P4 programming for custom offloads
Server, Cloud, Datacenter applications

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Hardware Block Diagram

OpenNIC Design

FPGA Design

Documents

Design Support

OpenNIC BitStream

Software

DPDK Patch

Features	Details
PCIe NIC Card Features	PCIe Gen3 x16 Host Interface 2 x 100GbE QSFP-DD Cages 254mm x 111.15mm, 3/4 Length, Full Height, Dual Slot with Active Cooling PCIe Card Quad/Dual Arm Cortex-A53 @1.5GHz, Dual Cortex-R5 @600MHz Up to 1143K Logic cells & 522K LUTs in FPGA programming logic. PS: 64bit, 8GB DDR4 RAM with ECC expandable up to 32GB PL: Dual 64bit, 8GB DDR4 RAM expandable up to 16GB 8GB eMMC Flash for Boot & OS storage expandable up to 128GB Micro SD Slot
Fintech Shell Features	Ultra-low-latency (< 350ns ) FPGA-based trading architecture Feedhandler for NASDAQ ITCH 5.0 and OUCH 5.0. Order entry and Order execution via TCP supported FPGA-based order-book management and Best Bid and Offer (BBO) tracking Hardware-accelerated user custom logic or Xelera Silva’s AI Inference trading strategy IP in market maker Host-side management of Xelera Silva AI models Integrated risk checks for order validation Hardware-based order generation and transmission Host side order history logging
OpenNIC Shell Features	Packet size 64 – 9600 bytes Line rate 2 × 100 Gbps/ 140 Mpps traffic burst (Packet size of 64 bytes), PCIe Gen3 Supported IPs are QDMA, CMAC, Packet Adapter, System Management Wizard, Clock Wizard Two User Logic Box of 250 MHz QDMA – Packet Adapter, 322MHz Packet Adpater – QDMA DMA engines operate based on the descriptors PS based solutions RTL plugins for AXI-lite interface and AXI4-stream interfaces Temperature – Voltage Monitor and control data transfer to SmartNIC
DPDK Software	Features Link status, speed and duplex configuration Promiscuous mode MTU update and Jumbo frame Flow control, Unicast MAC filter Fast mbuf free Timestamp offload and PTP TimeSync VLAN filter, SR-IOV Design L2 / L3 forward QoS framework Packet Generation IP Pipeline for flow classification / firewall / routing / segmentation / reassembly ACL – Access Control List management- Server / VMs Virtio-IO support for VMs/Containers/Dockers OpenVSwitch Crypto Framework IP-Sec Gateway Platform, Drivers and Applications OS and Supported Applications Operating System: Linux (RHEL OS, Ubuntu, Rocky Linux) Base application: DPDK, Python, Meson, Ninja Packet Generation: Pktgen-DPDK, TRex Packet Capture: Tcpdump & libpcap Software drivers: For an IOMMU enabled device: VFIO – PCI For legacy interrupts: IGB-UIO NIC standards IEEE 802.3 100G Ethernet

Fintech:

FPGA-based ultra-low-latency (< 350ns ) financial trading architecture
Feed handler for NASDAQ ITCH 5.0 and OUCH 5.0. Order entry and Order execution via TCP supported
Hardware-accelerated order-book management and Best Bid and Offer (BBO) tracking
Integrated trading strategy execution and risk checks in FPGA fabric
Hardware-based order generation and transmission

DYNANIC:

Uses NDK (Network Development Kit) Architecture
Contains Network module to handle Ethernet packet transmission and reception
Optimized for high throughput 100Gbps
A user-dedicated space in NDK firmware for application.

More info : https://cesnet.github.io/ndk fpga/devel/ndk_cards/iwave/g35p/readme.html

OpenNIC:

Contains QDMA, CMAC Subsystems, Packet Adapter, User Logic Box and User Plugins
Control and Data Interfaces
Network Data Transmission of 100Gbps
P4 Language for network acceleration

More Info : https://github.com/Xilinx/open-nic-shell

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FAQs

An FPGA-based programmable PCIe Accelerator NIC that offloads packet processing (L2/L3 forwarding, ACLs, QoS, security, custom workloads, AI Inference , Trading logic ) from the host CPU to hardware.

10/40G – (Zynq™ UltraScale+™, Arria® 10)
100G – Zynq™ UltraScale+™
200G – Agilex™ 7
400G – Agilex™ 7, Versal™ Premium
800G – Versal™ Premium Gen2

OpenNIC, Corundum, AVED and DYNANIC on AMD cards, NDK, Altera OFS and ASAF on Agilex cards.

Yes: SR-IOV, VirtIO, and Open vSwitch offload.

Yes, a bitstream and SW , design patch are provided as a part of deliverables.