UDP/IP Core

Name: UDP/IP Core
Brand: iWave Global
Availability: InStock

The UDP/IP Hardware protocol stack offloads UDP encapsulation task from the host processor enabling media streaming even in a processor less non-SoC designs, making it ideal for any standalone operation. This IP core provides an effective infrastructure to implement high-speed communication between the FPGA and other network devices. It supports easy to use AXI streams on the FPGA to connect to the network devices.

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High-Speed Ethernet on FPGA & SmartNIC

Features

Details

UDP/IP Core

Easy integration with 1G, 10G, 40G/50G, 100G, 200G and 400G Ethernet MAC
IPV4 support without packet fragmentation
Supports GMII/RGMII/SGMII/XGMII/XLGMII interfaces
Address Resolution Protocol (ARP) for proper functioning over the internet
UDP & IP checksum generation and validation support
Configurable AXI Stream interface with 8bit, 32bit, 64bit, 128bit, 256bit and 512bit width for transmission & reception of user data
32bit AXI4-Lite interface for handling control and status registers
Configurable buffer sizes for easy SoC integration
Supports optional Dynamic Host Configuration Protocol (DHCP) client
Supports optional Echo-Request & Reply messages (“ping”) of the Internet Control Message Protocol (ICMP) used to test network connectivity

ZU11/17/19 Dev Kit

iWave 100G UDP/IP core has been tested on AMD/Xilinx Zynq MPSoC FPGAs using iWave’s ZU11/17/19 based development kit. The QSFP connector on the carrier card provides a 100G Ethernet interface, enabling communication either with a host system supporting 100G UDP/IP or with another development kit for IP evaluation.
Integration Manual

Bring full UDP/IP connectivity to FPGAs even if no CPU is available
Offload UDP/IP processing into programmable logic
Enable media streaming with speed up to 100G
Offers a configurable number of UDP transmit and receive channels.