| SDR Based on RFSoC |
- FPGA Chipset: AMD RFSOC
- Channels: Up to 16 × 16 MIMO
- Tuning Range: DC – up to 2.3 GHz Direct sampling
- Instantaneous Bandwidth: Up to 2 GHz
- ADC sampling rate: Up to 5.9 GSPS, 14 bits
- DAC sampling rate: Up to 10 GSPS, 14 bits
- PCIe Bandwidth: Up to 128Gbps with Gen 4, x8 lane
- Form Factor: Full-Height Half-Length PCIe
- Multi-tile synchronization (MTS) with SYSREF inputs
- Configurable number of channels
- Dynamic tuning of the decimation and interpolation
- Burst mode or continuous modes data streaming
- Frequencies, channels, and signal chains configuration through host drivers
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| Software Stack |
- Robust Linux and Windows*** host OS support
- SDR Frameworks and Toolkits like GNU Radio and Pothos
- GPU Acceleration for Real-Time Processing
- Analysis and Visualization using GNU radio, Octave, SciPY, Python etc.
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| Host Interface |
- Full-Height Half-Length PCIe form factor, suitable for integration into Host PC systems.
- Linux OS (above 20.04), 16GB RAM minimum
- CPU 8 Core Minimum.
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