SD Memory Slave Controller

Name: SD Memory Slave Controller
Brand: iWave Global
Availability: InStock

Memory Slave Controller IP forms a bridge between the SD host and user interface, enabling the data transfer between each other. This IP will send the response to the SD host depending on the command issued and also communicates with the user through a register interface for control and status. The Controller has two different variants depending on the availability of the processor towards user side. One being the AXI4 -lite or AHB complaint interface for accessing through processor and other is simple general-purpose interface which can be used without the processor.

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Evaluation Platforms

ZED Board
iWave Actel
SmartFusion
Lattice Crosslink

Accessories

FMC Daughter Card

Features

Details

SATA Host Controller

Compliant with SD Physical Specification Version 3.00
Supports 1-bit and 4-bit SD Mode
Supports Standard and High Capacity operations
Supports Default and High Speed Modes of operation
Supports all mandatory slave registers set
CID Register fields are configured
Supports only Standard command set
Supports all mandatory SD Command Classes
CRC7 checking/generation for Command/Response
CRC16 checking/generation for Data transfer
Support Maximum block length of 512 bytes
Supports Single and Multiple block read and write data transfer
Supports Partial and Misalign Block length option
SD Memory only implementation
IP provides simple and general-purpose interface or AXI4-lite or AHB interface to user application

Highlights

Core handles SD bus protocol on the card interface and provides simplified interface to user logic
Core handle all the housekeeping tasks by itself without user logic intervention
Supports both processor and non-processor environments with two different variants
Supports both the standard and High capacity operation.

ZED Board

SD memory slave IP is tested in Zynq 7000 based devices from AMD/Xilinx using ZED Board and PMOD SD to interface with SD host using SD male to male custom cable. The baremetal version with DDR connected to FPGA targeted as memory variant of the IP is tested in this setup.

Integration Manual User Manual

iWave ProASIC3 custom dev kit

SD memory slave IP is tested in ProASIC3 based devices from Microchip using iWave’s ProASIC3 custom dev kit which has the built in SD connector to interface with SD host. The simple user Interface with Block RAM of FPGA targeted as memory variant of the IP is tested in this setup.

Integration Manual User Manual

SmartFusion2 Advanced Dev Kit

SD memory slave IP is tested in SmartFusion 2 based devices from Microchip using SmartFusion2 Advanced Development Kit (M2S150-ADV-DEV-KIT) and iWave FMC daughter card with SD to interface with SD host using SD male to male custom cable. The simple user Interface with Block RAM of FPGA targeted as memory variant of the IP is tested in this setup.

Integration Manual

Lattice Crosslink NX dev kit

SD memory slave IP is tested in Crosslink NX based devices from Lattice using Crosslink NX dev kit and PMOD SD to interface with SD host using SD male to male custom cable. The simple user Interface with Block RAM of FPGA targeted as memory variant of the IP is tested in this setup.

Integration Manual