Zynq™ UltraScale+™ XQ MPSoC 19/11EG System on Module – MIL Grade

• Quad/Dual Arm Cortex-A53 at 1.2GHz, Dual Cortex-R5 at 500MHz
• Arm Mali-400MP2 GPU @600MHz

Programming Logic (PL)

• Up to 1143K Logic cells and 522K LUTs
• PL GTY High Speed Transceivers x16 at 25.785Gbps
• PL GTH High Speed Transceivers x32 at 12.5Gbps

• PS GTR Transceiver Lanes x 2 (Up to 6.0Gb/s)
• GEM3 RGMII Interface or ULPI Interface x 1
• CAN Interface x 2

From PL Block

• High Speed GTH Transceiver Lanes x 12 (Up to 12.5Gbps)
• HD Bank IOs – Up to 46 Single Ended IO’s
• ADC Input pins- Up to 32 Single Ended IOs from HD Banks

• PS GTR Transceiver Lanes x 2 (Up to 6.0Gb/s)
• Gigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY)
• SD (4bit) x 1
• Debug UART and Data UART x 1
• SPI x 1(Optional)
• I2C x 2 Port
• JTAG x 1

From PL Block

• High Speed GTH Transceiver Lanes x 4 (Up to 12.5Gbps)
• HP Bank IOs – Up to 48 LVDS/96 Single Ended IO’s
• ADC Input pins – Up to 16 Differential/Single Ended HP Banks