PCIe to SD/MMC Bridge

iW-PCIe to SD/MMC Bridge is the IP core which converts the PCIe to SD or MMC bus interface. The interface towards the SD or MMC card is realized by the SD or MMC protocol implemented in the controller.

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Documents

Xilinx Evaluation Kit

Demo Link

Features Details
PCIe to SD/MMC Bridge  Compliant with SD Host Controller Standard Specification Version 2.0
Compliant with SD Physical Layer Specification Version 2.0
Compliant with eMMC Specification Version 5.1
Supports 1-bit,4-bit SD/eMMC modes and 8-bit eMMC modes.
Supports SD Card Detection input pin
Supports SD Card Write Protection input pin
Supports programmable clock frequency generation to the SD/eMMC card.
Supports Interrupt and ADMA2 transfer mode of operation.
Individual 2Kbyte data buffer for read and write.
Cyclic Redundancy Check (CRC) for command and data.
Supports timeout monitoring for response, data, CRC token & busy.
Supports a maximum block length of 2K-byte.
Supports both single block and multi block data transfer.
Supports power ON/OFF control to SD/eMMC card.
Supports Gen1 x1 PCIe link for host processor interface

 

  • Compliant with SD Host Controller Standard Specification Version 2.0
  • Compliant with SD Physical Layer Specification Version 2.0
  • Compliant with eMMC Specification Version 5.1
  • Supports Gen1 x1 PCIe link

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