Zynq™ Ultrascale+™ SmartNIC – 10G/40G

G30-XFibre-10/40G®

Full height, Half Length PCIe Card.
PCIe Gen3 x8 Host Interface
Single Front Panel 1x/4x 10GbE SFP+ Cages
Zynq Ultrascale+ ZU7 MPSoC
Linux driver & Data Plane Development Kit (DPDK)

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Hardware Block Diagram

Open Source NIC Design

OpenNIC Design

Documents

Design Support

OpenNIC BitStream

Software

DPDK Patch

Features	Details
PCIe NIC Card Features	PCIe Gen3 ×8 Host Interface 4 x 10GbE SFP+ cages Standard Full-Height, Half-Length, Single Slot with Active Cooling PCIe card PS: Quad Arm Cortex-A53 @1.5GHz, Dual Cortex-R5 @600MHz PL: 504K system logic cells ,230K LUTs, 312 BRAM, 96 Ultra RAM, 1728 DSP slices PS – Single 8GB, 64b + 8b ECC DDR4 Channel@ 2133 Mhz PL – Single 1GB, 16b DDR4 Channel @ 2133 Mhz Storage: 8GB eMMC Flash + microSD slot Connectivity/Debug: Micro-USB, JTAG header Dual Onboard Temperature Sensors One Wire Authenticator Onboard active fan
Fintech Shell Features	Ultra-low-latency (< 350ns )FPGA-based trading architecture Feedhandler for NASDAQ ITCH 5.0 and OUCH 5.0. Order entry and Order execution via TCP supported FPGA-based order-book management and Best Bid and Offer (BBO) tracking Hardware-accelerated user custom logic or Xelera Silva’s AI Inference trading strategy IP in market maker Host-side management of Xelera Silva AI models Integrated risk checks for order validation Hardware-based order generation and transmission Host side order history logging
System Requirements & Compatibility	PCIe Slot: Gen3 ×8 FHHL Disk Space: At least 50GB available RAM: Minimum 8GB BIOS Settings: Enable IOMMU, Hugepages, PCI Reallocation, Disable PCI-ASM Supported OS: Ubuntu 20.04, Ubuntu 22.04, RedHat 8 Supported Libraries & Applications: LinuxPTP, DPDK Platform, Drivers and Applications OS and Supported Applications Operating System: Linux (RHEL8 OS, Ubuntu) Base application: DPDK, Python, Meson, Ninja Packet Generation: Pktgen-DPDK, TRex Packet Capture: Tcpdump & libpcap Software drivers: For an IOMMU enabled device: VFIO – PCI
Corundum Shell Features	Packet Size 64 bytes to 9600 bytes Line Rate Performance: 1 × 10GbE 4 × 10GbE Supported IPs are PCIe Hard IP, Ethernet Transceiver IP and Application Block. User-programmable Application Block Region with dedicated control and streaming interfaces DMA engines operate based on descriptors. Hardware checksum offload, VLAN tagging and RSS (flow hashing). Integrated Linux kernel mode driver for seamless netdev stack integration.
OpenNIC Shell Features	Packet Size 64 bytes to 9600 bytes Line Rate Performance: 1 × 10GbE 4 × 10GbE Supported IPs are QDMA, MAC, Packet Adapter, System Management Wizard, Clock Wizard. PL based solutions Two dedicated User Logic boxes (250 MHz QDMA – Packet Adapter, 322 MHz Packet Adapter – MAC) DMA engines operate based on the descriptors AXI-based 10G and 40G MAC subsystem PCIe-compliant scatter/gather transfers are supported through the Xilinx QDMA engine, validated for both 10GbE and 40GbE configurations. RTL plugins for AXI-lite and AXI4-stream interfaces Monitoring Temperature and voltage with dynamic control of data transfer to the SmartNIC.
*DPDK Software	Features Link Status, speed and duplex configuration Promiscuous mode MTU updates with Jumbo frame support Flow control, Unicast MAC filter Fast mbuf free VLAN filter, SR-IOV Design L2 / L3 forward QoS framework Packet Generation IP Pipeline for flow classification / firewall ACL – Access Control List Crypto Framework NIC Standards IEEE 802.3 10G, 40G Ethernet

OpenNIC:

Contains QDMA, MAC Subsystems, Packet Adapter, User Logic Box and User Plugins
Control and Data Interfaces
Network Data Transmission of 10/40Gbps

More Info : https://github.com/Xilinx/open-nic-shell

Open Source NIC Design (Corundum):

Supports PCIe Hard IP, Ethernet Transceivers IP and Application Block.
User-programmable Application Block Region with dedicated control and streaming interfaces.
DMA engines operate based on descriptors.
Hardware checksum offload, VLAN tagging and RSS
Integrated Linux kernel mode driver.

More Info : https://github.com/corundum/corundum

Fintech:

FPGA-based ultra-low-latency (< 350ns ) financial trading architecture
Feedhandler for NASDAQ ITCH 5.0 and OUCH 5.0. Order entry and Order execution via TCP supported
Hardware-accelerated order-book management and Best Bid and Offer (BBO) tracking
Integrated trading strategy execution and risk checks in FPGA fabric
Hardware-based order generation and transmission

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FAQs

An FPGA-based programmable PCIe Accelerator NIC that offloads packet processing (L2/L3 forwarding, ACLs, QoS, security, custom workloads, AI Inference , Trading logic ) from the host CPU to hardware.

10/40G – (Zynq™ UltraScale+™, Arria® 10)
100G – Zynq™ UltraScale+™
200G – Agilex™ 7
400G – Agilex™ 7, Versal™ Premium
800G – Versal™ Premium Gen2

OpenNIC, Corundum, AVED and DYNANIC on AMD cards, NDK, Altera OFS and ASAF on Agilex cards.

Yes: SR-IOV, VirtIO, and Open vSwitch offload.

Yes, a bitstream and SW , design patch are provided as a part of deliverables.