| Hardware Specification |
- Front Panel consists of four Nos of 10Gbps SFP+
- PCIe Gen 3.0 x8 lane Endpoint mode
- 2Nos of High speed XMC VITA42.0 Connector to support 8-lane PCIe Gen3.0
- DC Input : 3.3V via XMC connector
- Operating Temperature : -40C to +85C
- Form Factor : Standard XMC formfactor (74mm x 149mm)
- Cooling : Conduction cooled with Aluminium enclosure
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| Host Interface |
- PCIe Gen 3, x8 lane with a total maximum theoretical bandwidth of 64Gbps.
- Full-Height Half-Length PCIe form factor, suitable for integration into Host PC systems.
- Supports Linux OS
- 16GB RAM and CPU 8 Core Minimum.
- SW deliverable includes APIs and test applications
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| Software Specification |
- Supports low-level drivers for Linux operating systems enabling the host CPU to control the hardware and manage data transfers
- C/C++ APIs enable link control, allowing users to enable sFPDP links and configure the required link speeds
- FIFO management is supported through software, with C/C++ APIs to set, control, and read FIFO threshold levels for reliable data handling.
- FPDP signal monitoring and control is provided via C/C++ APIs to set and read the status of signals such as PIO1, PIO2, DIR, NRDY, and related control lines
- C or C++ APIs provides functions for advanced feature control and status reporting is available for CRC checking, flow control, copy, and copy-loop operating modes.
- Supports the APIs that allow streaming high volumes of data across multiple sFPDP channels directly into host memory
|
| Host Interface |
- PCIe Gen 3, x8 lane with a total maximum theoretical bandwidth of 64Gbps.
- Full-Height Half-Length PCIe form factor, suitable for integration into Host PC systems.
- Supports Linux OS
- 16GB RAM and CPU 8 Core Minimum.
- SW deliverable includes APIs and test applications
|
| Highlights |
- Compliant with sFPDP VITA 17.1, with a seamless upgrade path to VITA 17.3
- The XMC form factor provides a rugged design and enables seamless integration into embedded computing platforms
- Designed for high-speed, low-latency, and deterministic data transfer, ideal for real-time systems
- Supports a broad range of programmable line rates from 1.0625 Gbaud to 6 Gbaud
- Four independent sFPDP channels, implemented using four 10 Gbps SFP+ interfaces for scalable throughput
- Powered by iWave’s in-house sFPDP IP core, ensuring reliability, flexibility, and long-term support
- Enables simultaneous multi-stream data acquisition and transfer without performance degradation
- Optimized for defence, aerospace, and high-performance data acquisition applications
- FPGA-based architecture allows future feature expansion and customization
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