In today’s embedded systems, data bandwidth is a bottleneck. Traditional parallel interfaces demand wide buses, multiple layers, and complex PCB routing. What if you could achieve high-speed, low-latency serial links with minimal resources and without the overhead of Ethernet or PCIe?
At iWave, we have validated Aurora across our entire Zynq™ UltraScale+™ MPSoC System on Module (SoM) portfolio from ZU1 to ZU19 enabling customers to build robust, production-ready systems faster.
What is Aurora?
Aurora is a scalable, link-layer protocol for point-to-point serial communication. It runs over FPGA high-speed transceivers (GTP/GTX/GTH/GTY) to provide reliable bandwidth with minimal logic footprint.
- Aurora 8B/10B: Simplicity and broad compatibility
- Aurora 64B/66B: Higher efficiency (~3% overhead) and faster throughput
Aurora channels can consist of one or more lanes, each being a high-speed serial connection. With channel bonding, multiple lanes are synchronized to form a wider, higher-throughput data path. Full-duplex operation ensures simultaneous transmit and receive, while simplex mode supports efficient uni-directional links.
The image illustrates a high-level architecture of a full-duplex Aurora communication system, enabling high-speed serial data transfer between two user applications.
On each end, user logic interfaces with the Aurora IP core through a parallel data path known as the user interface. The Aurora core handles the encoding of user data into a compact, low-overhead 8B/10B or 64B/66B format, suitable for transmission over serial transceivers. Data travels across multiple Aurora lanes, which are individual high-speed serial links using FPGA transceivers (such as GTH or GTY), and these lanes are logically grouped into what is called an Aurora channels. The channel bonding process ensures the alignment and synchronization of data across lanes. Operating in duplex mode, the system supports simultaneous transmission and reception, allowing bi-directional communication.
Aurora Transmitter (TX Path)
In a high-speed transmitter, the data path passes through several key stages to ensure reliable transmission.
First, a scrambler randomizes the outgoing bit stream to maintain good transition density and reduce noise. The data is then processed by the 8B/10B or 64B/66B encoder. The 8B/10B encoder maps each 8-bit data or control character into a 10-bit symbol, providing DC balance and enough transitions for clock recovery. In contrast, 64B/66B adds a 2-bit sync header to 64 bits of payload, reducing overhead while maintaining synchronization.
Next, framing and optional CRC insertion provide flow-control symbols or error detection capability, ensuring data integrity and proper packet delimiting. The stream is then passed through a gearbox and alignment unit, which adjusts the parallel data width to match the serial interface requirements of the physical layer and guarantees correct word alignment.
Finally, the GT transceiver (GTH/GTY) serializes the parallel data into a high-speed bit stream, applies equalization for signal integrity, and transmits it over the physical medium.
Aurora Receiver (RX Path)
In a high-speed receiver, the incoming serial data first passes through a Deserializer with Clock Data Recovery (CDR), which recovers the embedded clock and converts the serial bit stream into parallel data.
The alignment detector then identifies the 10 or 66-bit frame boundaries, ensuring proper synchronization with the transmitted frames. Next, the 8B/10B or 64B/66B decoder removes the 2-bit sync headers and extracts the original 8 or 64-bit user data from each 10 or 66-bit block.
Finally, a descrambler restores the original data pattern, reversing the scrambling applied at the transmitter, and delivering clean, correctly ordered data to the MAC or higher-layer logic.
Applications of Aurora core
- Chip-to-chip links: Replace wide parallel buses, cut trace count and PCB layers
- Board-to-board and backplane links: Leverage existing cabling and backplanes; scale lanes/line rate as needed.
- Simplex connections (unidirectional): Alternate initialization enables one-way links without a back-channel.
Portfolio of MPSoC System on Moduls from iWave:
- Zynq UltraScale+ ZU19/ZU17/ZU11
- Zynq UltraScale+ ZU15/ZU9/ZU6
- Zynq UltraScale+ ZU7/ZU5/ZU4
- Zynq UltraScale+ ZU5/ZU4/ZU3T/ZU3/ZU2/ZU1
iWave is a global leader in the design and manufacturing of FPGA System on Modules and ODM Design Services. With over 25 years of diverse experience in the FPGA domain and a strong design-to-deployment competence, iWave strives to transform your ideas into time-to-market products with reliability, cost, and performance balance.
iWave provides a robust suite of tools, libraries, and software resources that empower developers to harness the full potential of the Zynq™ UltraScale+™ MPSoC System on Modules. The System on Module are go-to-market and production-ready, complete with documentation, software drivers, and a board support package.
For more information about the Zynq™ UltraScale+™ MPSoC SoM/Development Kit, and iWave capabilities, please visit www.iwave-global.com or contact us at mktg@iwave-global.com.
