Documents
Design Support
Software
| Features | Details |
|---|---|
| SoC | Versal RF Series Adaptive SoC VR1602/1652/1902/1952. Processing System (PS)
Programming Logic (PL)
AI Engine (AIE)
|
| RAM Memory | Dual Channel (2x16bit) 8GB LPDDR5x from PS. Dual Channel (2x16bit) 8GB LPDDR5x from PL. Two Single Channel (32bit), 8GB LPDDR5x from PL. |
| Storage | 256MB OSPI Flash for Booting. 32GB eMMC Flash for Storage. Micro SD slot for PS. 2Kb EEPROM. |
| ADC Channels (Up to x16) | 1 x Right Angle SMPM Connector on Front Panel with Balun (BW 2GHz to 50GHz). 1 x Straight Angle SMPM Connector with Balun (BW 2GHz to 50GHz). |
| DAC Channels (Up to x16) | 1 x Right Angle SMPM Connector on Front Panel with Balun (BW 2GHz to 50GHz). 1 x Straight Angle SMPM Connector with Balun (BW 2GHz to 50GHz). |
| Clock & PLL | Fully Configurable Clock Synthesizer with SyncE and PTP support. Integrated Configurable ultra-low noise PLL for ADC & DAC(Optional). 6 x SMA Straight connector for clocks (10MHz_IN, 10MHz_OUT, 1PPS IN, 1PPS_OUT, Synchronous Clock_INP/N). |
| Host Interface | Up to PCIe Gen4 x8 Edge Connector |
| Expansion | FMC+ High serial Pin connector (HSPC) Connector. 4 channel GTM2 Transceivers @ up to 56Gbps/112Gbps. 1 GTM2 Reference clock. 57 LVDS IOs/114 Single ended (SE) IOs from PL Banks. |
| Others | Single QSFP- DD Connector up to 200G/400G Support on Front Panel. 2 x RJ45 1GbE Ethernet Port on Back Panel from PS. USB 2.0 through USB -Type-C Connector from PS. RTC Battery Header. |
| Debug | Integrated JTAG Programming/Emulator Module. USB Type C Debug Port on Front Panel for PS Debug UART, PL DATA UART and JTAG. |
| Thermal | Fan sink (by default) |
| Operating Temperature | -40°C to +85°C (Industrial) |
| Power | 75W max from PCIe x 8 Host. 12V Input from 8Pin ATX Power Connector in Back Panel Power Droop Sharing (to maximize power when needed) Power dissipation is application dependent. |
| Form Factor | 254mm x 125.31mm (¾ Length PCIe*) |



