The above figure shows the block diagram of the Corundum NIC, which is organized into multiple hierarchical levels. At the highest level, the design integrates various support and interface components. These include the PCI Express hard IP core and Ethernet interface blocks such as MACs, PHYs, and serializers along with an instance of the wrapper code for the core of the FPGA that connects the NIC to the host system via a DMA interface.

At the heart of the Corundum NIC architecture, the application block serves as a flexible and powerful integration point for custom packet processing, in-network computing, and application-specific logic. This block is designed to interface seamlessly with multiple internal NIC subsystems, enabling developers to implement features such as filtering, traffic shaping, real-time analytics, or offload engines directly in the data path. Its modular design allows rapid prototyping of advanced networking applications, particularly in research and data center environments where programmability is key.

Architectural Adaptation and Implementation

Adapting Corundum to the iW-Fibre SmartNIC involves aligning the Corundum NIC pipeline and modules to the hardware resources and interfaces available on the iWave platform. Key architectural design elements include:

FPGA Fabric Integration: Corundum’s HDL design was optimized and coded for iWave’s FPGA, taking advantage of the Xilinx Ultrascale+ architecture. Particular emphasis was placed on timing closure and resource usage, such as DSP blocks, BRAM, and transceivers.

Physical Interface (PHY) Adaptation: The iW-Fibre SmartNIC platforms support up to 4 SFP+ or 1 QSFP modules. SmartNIC platforms equipped with SFP+ modules were utilized to support 10G and 40G Ethernet links, while those featuring QSFP ports enabled connectivity for 100G Ethernet links.

PTP Support: PTP enables highly accurate clock synchronization across distributed systems in a network. Corundum supports hardware timestamping and clock synchronization features, ensuring that the NIC can participate in or even act as a master or slave clock in PTP domains. Its implementation enables precise alignment of packet timestamps and deterministic behavior, which is essential for latency-sensitive applications.

Software Stack Adaptation: On the software side, drivers and firmware were ported and optimized to interact with the iWave platform. Linux kernel modules based on the Corundum reference driver were modified to support the iWave device IDs, register maps, and platform-specific initialization routines. This ensured proper enumeration and control of the NIC within the host system.

DPDK Applications: The high-performance packet I/O of Corundum on iWave was validated with DPDK applications. These user-space apps bypass the kernel stack to achieve low-latency, high-throughput networking by directly accessing NIC queues through memory-mapped I/O. The integration of DPDK into the application block of the Corundum design enabled performance testing with tools like DPDK-Pktgen and TestPMD, and supported key use cases such as L2/L3 forwarding, firewall functionality, encryption/decryption, and multi-stage packet pipelines.

Features and Capabilities of the implementation

High-Speed Network Connectivity: The integration fully supports 10G, 40G and 100G Ethernet links, achieving line-rate packet processing with minimal latency.

Fully Programmable Packet Pipeline: Corundum’s modular pipeline enables customization of parsing, filtering, and forwarding packet logic.

DMA and Zero-Copy Data Transfer: The PCIe Gen3 interface with DMA engines provides efficient data transfer between NIC and host memory.

Hardware Offloads: The implementation supports a suite of offload capabilities such as:

• • Checksum computation (IPv4, TCP, UDP)
  • VLAN tagging/stripping
  • Packet filtering and classification
  • Receive Side Scaling (RSS)

Data Throughput Analysis

Performance tests were conducted using iperf3 on the G30-XFibre-10/40G Platform to validate the Corundum NIC implementation.

The tests validated line-rate performance across all configurations. The 40G setup achieved 37 Gbps aggregate throughput with consistent performance on each port and each core, confirming efficient multi-port handling and DMA implementation.

Converting the open-source Corundum NIC to the iW-Fibre SmartNIC platform produces a solid, programmable network interface solution. By matching Corundum’s versatile architecture with iWave’s high-performance FPGA hardware, this integration provides a feature-rich, scalable, and efficient NIC for today’s demanding data center environments.

For more information about iWave’s SmartNIC platforms and its features contact mktg@iwave-global.com