Remote Direct Memory Access (RDMA) has become a critical enabler for modern high-performance systems across datacentres, telecommunications, storage, and real-time data acquisition. By allowing two systems to exchange data directly between their memory spaces without CPU intervention, RDMA drastically reduces latency, minimizes overhead, and achieves near-line-rate throughput.
iWave’s RoCEv2 (RDMA over Converged Ethernet) IP Core brings these capabilities to FPGA and SoC platforms, providing a complete, efficient, and high-speed data-movement engine that delivers both raw performance and robust interoperability across Ethernet networks.
Developed to meet demanding data-plane workloads, iWave’s RoCE IP integrates seamlessly with supporting IP blocks such as UDP/IP, DMA, and high-speed Ethernet MACs. This makes it a complete, production-ready solution for applications requiring deterministic behaviour and real-time transfer capabilities.
What the iWave RoCE IP offers
- RoCEv2 support (routable RoCE): iWave’s cores implement RoCEv2 packet formats (Ethernet + IP + UDP + InfiniBand payload), enabling routable RDMA across Layer-3 networks and larger topologies. This expands deployment beyond a single Ethernet broadcast domain.
- High throughput: iWave publishes a RoCEv2 IP variant designed for multi-100G network interfaces and datacentre-class links, combined with complementary UDP/IP cores for packet encapsulation.
- Low-latency, zero-copy operation: The IP stack is engineered to support RDMA semantics (direct memory access, kernel bypass) so data transfers avoid CPU copies and drastically reduce latency compared with socket-based approaches.
- Integration-friendly building blocks: iWave supplies related cores (UDP/IP, DMA engines and bridges) allowing a full data path from network interface through FPGA fabric to host memory. This reduces integration time and risk.
iWave’s RoCEv2 IP — Architecture and Building Blocks
The RoCEv2 IP architecture integrates cleanly into FPGA-based systems and consists of the following subsystems:
- Memory and DMA Interface: The IP can work with AXI DMA engines, on-chip memory, or external DDR, depending on system architecture. This flexibility simplifies host-side integration.
- RoCE Transport Layer Engine: Implements packet formatting, RDMA operations, sequencing, acknowledgements, and retransmissions. It manages QPs and session-level state machines to ensure reliable transport.
- UDP/IP Offload Engine: Handles packet encapsulation for RoCEv2. When paired with iWave’s standalone UDP/IP core, the solution becomes fully routable, allowing use in diverse network topologies.
- iCRC and Integrity Unit: Implements the mandatory invariant CRC calculations, crucial for RoCE compliance and interoperability with standard NICs and switches.
- High-Speed Ethernet Interface: The IP supports high line rates, including multi-100G implementations depending on the FPGA device and chosen MAC/PHY.
RoCEV2 Packet format
The RoCEv2 packet format encapsulates RDMA traffic within UDP/IP, where the RDMA transport headers (such as Base Transport Header and optional extensions) follow the standard UDP and IPv4/IPv6 headers. This structure enables routable, low-latency RDMA communication while leveraging conventional Ethernet and IP networks.
Key technical benefits
- Reduced CPU overhead: Offloading RDMA operations to FPGA fabric frees host CPU cycles for application logic, improving system-level throughput and latency determinism.
- Scalable across topologies: By supporting RoCEv2, iWave’s solution can be used across routed IP networks — important for distributed systems and multi-rack deployments.
- Modular & configurable: The IP is designed to be configurable for target FPGA families and interface widths; iWave provides documentation and customization options to fit specific board-level constraints.
- Proven Solution: The RoCEv2 IP has been validated on a standard off-the-shelf NIC card from NVIDIA, Intel etc, demonstrating reliable RDMA connectivity with low latency and high throughput performance.
Typical use cases
- Data-centre acceleration: High-speed data movement between servers, NVMe fabrics, or between NICs and accelerators for storage and AI workloads.
- Telecom & 5G infrastructure: Real-time packet processing where deterministic, low-latency buffer transfers are required.
- Test & Measurement Equipment: Data acquisition units, and signal processing devices capture and stream multi-gigabit samples to hosts for real-time analysis.
- Software-Defined Radio (SDR) Platforms: High-rate I/Q samples can be streamed to host memory with microsecond latency—ideal for RFSoC and FPGA-based wideband SDR systems.
- Video and Imaging Pipelines: High-resolution imaging sensors and video analytics engines can transfer multi-gigabit frames across nodes without CPU overhead.
Support, licensing & delivery
iWave offers IP licensing and delivery models typical for FPGA IP vendors: RTL/netlist delivery, documentation, example testbenches, and support for porting to different FPGA families. They also provide complementary IP (UDP/IP core, PCIe bridges, etc.) to enable a full-stack solution rather than a disjointed set of blocks. Contacting iWave for licensing terms, porting services, and evaluation options is recommended early in any integration project.
Conclusion
iWave’s RoCEv2 IP solution brings the full power of RDMA to FPGA and SoC environments, enabling high-speed, low-latency, and scalable data movement across Ethernet networks. With a complete ecosystem of supporting IP blocks and strong customization capability, the RoCEv2 IP is an ideal fit for modern computing, telecom, storage, SDR, and real-time data systems.
Its combination of performance, reliability, and integration readiness makes it a robust choice for engineers looking to accelerate data-plane workloads and build high-throughput applications on FPGA platforms.
