November 3, 2025
Article
Programming Protocol-independent Packet Processors (P4) is a dynamically developing language aimed at programming network data planes. It has significantly contributed to the research of modern networking by promoting more versatile and adaptable network control. Unlike conventional systems where vendors of devices determine function, P4 enables programmers to describe what happens to packets. P4 also offers benefits such as protocol independence, target flexibility, and field reconfigurability. Using P4 IP within the iW-Fibre SmartNICs framework enables the development of high-performance and configurable pipelines, supporting diverse network functions at line rates.
In iW-Fibre SmartNICs P4 integration transforms programmable packet logic into hardware-accelerated functions. The compiled P4 IP is integrated into the FPGA shell, enabling customizable pipelines and efficient hardware offloading. The following steps outline the build process
The P4 Architecture can be divided into three modules:
Building P4 IP on the iW-Fibre SmartNIC involves P4 compilation, hardware integration, and software setup, resulting in a fully functional, protocol-independent pipeline capable of line-rate packet processing.
The P4 compiler is used to generate the P4 IP for the iW-Fibre card, translating high-level P4 programs into RTL, and control files for hardware–software integration. The required inputs include the P4 programming code, which defines packet processing and offload logic, and the Architecture P4 code, which specifies the pipeline structure. The compiler outputs System Verilog (.sv) RTL files and control files that describe LUT names, configurations, and pipeline details. These control files are also used in user space to manage LUT entries, such as adding, deleting, or modifying them as needed.
In the hardware integration phase, the P4 IP is integrated into the FPGA design shell using IDE Vivado (Xilinx) or Quartus (Altera). The key inputs include P4 RTL files from the compiler and the FPGA shell RTL files (e.g., OpenNIC or ASAF). These are combined to generate the FPGA shell binary, which is then loaded onto the iW-Fibre card for deployment.
The Software Configuration, performed on the host system, allows users to manage P4 LUTs such as adding, deleting, or modifying entries in the P4 IP by compiling the Control plane Software application with the Control files generated from the P4 compiler.
The Data Plane manages packet transfer between interfaces. In P4, packets from the network or host are distributed across multiple FPGA pipelines with the help of multiplexer, where each pipeline processes them using LUT entries and P4 externs. After processing, a demultiplexer combines the results and forwards the packets to their destination.
3. Control plane:
The Control Plane defines how packets should be processed and forwarded in the network. With P4, much of this processing is now offloaded to the Data Plane, allowing the Control Plane to focus primarily on updating the Lookup Table (LUT) entries and some P4 externs.
Key components:
In conclusion, iWave SmartNICs provide a robust and seamless platform for P4 development, uniting the flexibility of software programmability with the speed of hardware acceleration. This integration empowers developers to build customized, high-performance, and scalable packet processing solutions. With their protocol-independent architecture, iWave SmartNICs enable rapid deployment of new features and protocols without the need for hardware to redesign.
For more information feel free to contact us at mktg@iwave-global.com
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