Modern data centers increasingly rely on SmartNICs not only to accelerate networking functions but also to offload compute-intensive workloads such as encryption, compression, telemetry, and real-time analytics. Rather than using a fixed datapath NIC, using a framework like Open FPGA Stack (OFS) allows developers to build highly tailored FPGA-based accelerators that plug into a SmartNIC form factor.
The Open FPGA Stack (OFS) is an open, modular framework that supports building reusable FPGA shells and Accelerator Functional Units (AFUs). By adapting OFS for the iW-Fibre SmartNIC, developers can combine the high-bandwidth hardware of iWave’s design with OFS’s flexible development ecosystem, enabling rapid creation and deployment of custom acceleration pipelines.
What is Open FPGA Stack?
OFS is a complete hardware–software framework for FPGA accelerator development. It provides:
- A modular FPGA Interface Manager (FIM) which acts as the shell of OFS that implements clocks, resets, memory controllers, PCIe interfaces, and Ethernet interfaces.
- A well-defined partial reconfiguration region where developers implement AFUs dynamically without reloading the static shell.
- A software stack composed of:
- The Linux Device Feature List (DFL) driver framework
- The OPAE-SDK, which provides user-space APIs and tools for bitstream management, device enumeration, and AFU control.
- Board management controller for power sequencing and voltage telemetry.
In essence, OFS standardizes the lower layers of FPGA platform integration so developers can focus on accelerator logic rather than board-level bring-up.
The above block diagram illustrates how an OFS-based FPGA design is divided into a static FIM region and a dynamic AFU (Accelerator Functional Unit) region. The FIM provides all board-level infrastructure including PCIe, memory controllers, transceivers, clocks, resets, and management logic ensuring stable system operation and a consistent interface. The AFU region is the user-programmable portion where custom accelerators or datapaths are implemented. This separation allows developers to reuse the shell across platforms and update AFUs independently, supporting partial reconfiguration and streamlined accelerator development.
Within the FIM, the following key components have been used:
- PCIe Subsystem.
- Memory Subsystem
- High-Speed I/O Transceivers
- FPGA Management Engine (FME) and Board Management Controller (BMC)
- Interfaces to AFU Region
The dynamic AFU region provides a configurable space where custom workload designs can be implemented. OFS includes example templates that developers can use as a starting point, and AFUs may also be deployed through the partial reconfiguration (PR) flow. In the default configuration, this PR region contains host exercisers for validating memory (HE-MEM) and Ethernet (HE-HSSI) interfaces on the SmartNIC platform. These exercisers can be removed and replaced with user-defined AFUs without affecting the operation of the static FIM, which continues to maintain platform infrastructure and PCIe presence. Within this region, developers can integrate a range of functions, such as high-speed Ethernet MACs, encryption/decryption blocks, telemetry modules, data transformation pipelines, key-value processing engines, security offload components, custom protocol or low-latency streaming logic, and host memory access using PCIe DMA.
Architectural Adaptation and Implementation
To adapt OFS to the iW-Fibre platform, the design maps into two major regions: the static FIM and the dynamic AFU region.
- OFS FIM (Static Region)
| Component | iW-G51P | iW-G43P |
|---|---|---|
| FPGA | FPGA Agilex 7 F-series (2xF-tile) PCIe Attach OFS design Agilex 7 I-series (R-tile + F-tile) PCIe Attach OFS | Agilex 7 I-series (R-tile + F-tile) PCIe Attach OFS |
| PCIe | Gen-4 F-tile PCIe endpoint | Gen-5 R-tile PCIe endpoint |
| Ethernet | Front Panel QSFP-DD Cage (200G/100G Ethernet Subsystem) | QSFP56-DD Cages (400G/200G Ethernet Subsystem) |
| DDR Memory | Hard Processor System (HPS) memory: 8GB DDR4, x72 (with ECC), 3200 MHz FPGA Memory: Single Fabric 8GB DDR4 channels, x72 (with ECC), 3200 MHz | Hard Processor System (HPS) memory: 8GB DDR4, x72 (with ECC), 3200 MHz FPGA Memory: Dual Fabric 8 GB DDR4 channels, x72 (with ECC), 3200 MHz |
| Board Management Controller | – | The G43P SmartNIC platform includes the Intel MAX10 BMC |
This ensures a hardware-compatible base for AFU development.
The dynamic AFU region can be designed with the required functionality with the help of AFU developers.
- OPAE-SDK
The primary software interface between user applications and the FPGA.
Key capabilities include:
- AFU enumeration
- Bitstream loading (static or partial)
- Memory allocation and function mapping (PF and VF binding)
- Status and health reporting
- Debug and configuration utilities
OPAE tools such as fpgainfo, fpgaconf, fpgasupdate and fpgadiag streamline SmartNIC management and deployment of bitstream images.
- Linux DFL Drivers
DFL exposes FPGA regions as discoverable features:
- The FIM is mapped as the core FPGA region
- Each AFU appears as a separate feature
This allows seamless interaction between the iW-Fibre FPGA logic and host software stacks.
Validation Results
The snapshots shown illustrate the hardware details and memory test results obtained after porting the OFS design onto the iW-Fibre SmartNIC platform. Using fpgainfo command, the PHY status of the SmartNIC.
The Host Exerciser output shows HE-MEM test, which validates and benchmarks the data path between the host and the FPGA-connected DDR memory across different throughput configurations.
Adapting the Open FPGA Stack to the iW-Fibre SmartNIC platform combines a modular FPGA framework with high-performance networking hardware. This integration provides a reusable FPGA shell and supports dynamic AFU updates through partial reconfiguration without interrupting system operation. With high-bandwidth capabilities and support from the OPAE and DFL software stack, the platform enables customizable accelerators for workloads such as low-latency packet processing, compute offload, and security functions, making it suitable for heterogeneous data center environments.
