| SDR Based on RFSoC |
- FPGA Chipset: AMD ZU19/ZU17/ZU11EG MPSOC
- RF Transceiver: AD9361
- Channels: RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
- TX band: 47 MHz to 6.0 GHz
- RX band: 70 MHz to 6.0 GHz
- Tunable channel bandwidth: <200 kHz to 56 MHz
- Data Plane Bandwidth: Up to PCIe Gen3 x8 or up to 40G ethernet using iWave UDP IP/RoCEV2 IP core or up to 40G Aurora/ sFPDP
- Deterministic multi-channel synchronization using SYSREF-aligned JESD204B/C interfaces
- Configurable number of channels
- Dynamic tuning of the decimation and interpolation
- Burst mode or continuous modes data streaming
- Frequencies, channels, and signal chains configuration through host drivers
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| Software Stack |
- Robust Linux and Windows*** host OS support
- SDR Frameworks and Toolkits like GNU Radio and Pothos
- GPU Acceleration for Real-Time Processing
- Analysis and Visualization using GNU radio, Octave, SciPY, Python etc.
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| Host Interface |
- FPGA/GPU/CPU-based processing cards for real-time signal processing, AI acceleration, and high-bandwidth data handling.
- Supports VPX fabric interfaces including PCIe, Ethernet, Aurora and sFPDP for scalable system integration.
- Supports Linux-based host systems with PCIe/Ethernet connectivity for SDR control and configuration
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