ZU11/ZU17/ZU19EG Quad Port PXIe Module

• • CLK100 / SYNC100 and PXI_CLK10 timing signals for multi-module synchronization
  • I2C / SMBus for system and platform management
  • GA[0:4] geographic addressing for chassis slot identification

Front Panel

• • 4 × SFP28 ports, supporting up to 25 Gb/s per port

On-board Headers

• • JTAG header for FPGA configuration and debug
  • Debug UART header
  • 18 GPIO pins
  • 1 × ARINC 429 interface on DB9 connector
  • 1 × RS-422 interface on DB9 connector

• • Quad/Dual Arm Cortex-A53 @1.5GHz, Dual Cortex-R5 @600MHz
  • Arm Mali-400MP2 GPU @677MHz

Programming Logic (PL)

• • Up to 1143K Logic cells & 522K LUTs

Memory

• • 64bit, 4GB DDR4 RAM for PS with ECC (Expandable)
  • 64bit, 4GB DDR4 RAM for PL (Expandable)
  • 8GB eMMC Flash (Expandable up to 128GB)

• • PCIe Gen 3, x8 lane over the PXIe backplane with a total maximum theoretical bandwidth of 64 Gbps
  • 100 MHz PCIe reference clock (REFCLK) sourced from the backplane

• • XMC 2.0 (VITA 42/VITA 61) module site
  • Connector J15: PCIe x8, REFCLK, module power, JTAG and GA[0:4]
  • Connector J16: PXIe timing clocks, I2C / SMBus / IPMB-L, debug UART, GPIO, RS-422 and ARINC 429

• • Powered from PXIe backplane 12 V, 3.3 V and 5 V_AUX rails
  • On-board protection and filtering circuit
  • Supplies +12 V / -12 V, VPWR, 3.3 V and 3.3 V_AUX to the XMC

• • 3U PXI Express peripheral module, suitable for integration into standard PXIe chassis

• • Forced-air cooling through PXIe chassis airflow