The rapid growth of data intensive applications has accelerated the adoption of 100G Ethernet across industries. From financial trading & broadcast systems to AI clusters and high performance computing, organizations require networking solutions that combine maximum throughput with deterministic, low latency performance. iWave addresses these demands with its fully in house developed FPGA based 100G UDP/IP Stack, delivering a complete networking solution implemented entirely in FPGA logic for Ethernet communication.
Key Features
iWave’s UDP/IP 100G IP core stack is designed for seamless integration and broad compatibility across Ethernet standards. Notable features include:
- Multi-speed Ethernet support: Compatible with 1G, 10G, 40G, and 100G Ethernet MACs
- Interface flexibility: Supports GMII, RGMII, SGMII, XGMII, and XLGMII interfaces
- IPv4 support without packet fragmentation
- ARP (Address Resolution Protocol) for proper internet-layer functioning
- UDP & IP checksum generation and validation
- Configurable AXI Stream interface: Data widths of 8-bit, 32-bit, 64-bit, 128-bit, 256-bit, and 512-bit for user data transmission and reception
- 32-bit AXI4-Lite interface for control and status register access
- Optional DHCP client support for dynamic host configuration
- Optional ICMP Echo-Request & Reply (“ping”) support for network connectivity testing
Demo Setup 1: Board-to-Host
Overview: In this configuration, an FPGA board is connected to a host machine equipped with a Mellanox ConnectX 100G NIC. This setup showcases interoperability with a commercial 100G network interface card. Packets are transmitted from the FPGA to the host, received by a user-space application, and forwarded back to the FPGA.
Figure 1: Board to Host Demo Setup
Board Initialization: Once the design is programmed onto the FPGA, the RX Status register is checked to confirm that the link is up. The terminal then displays the assigned MAC address, IP address, and available menu options for the user.
Figure 2: Board Initialization
Host Configuration: On the host machine, the ifconfig command is used to display the two network interfaces of the Mellanox NIC. A packet generator and traffic analyzer application is then launched, which provides visibility into link status, available options, RX and TX packet counts, line rate, and received packet sizes.
Figure 3: Host configuration
Transmission: From the FPGA menu, the user selects Option 1 to initiate UDP transmission. Parameters such as stream size and transmission type (continuous or packet-based) are entered, and the protocol is set to UDP.
On the host side, packets can be observed being transmitted and received on Port 0 of the Mellanox NIC, along with line rate utilization and the maximum number of packets received per second.
Figure 4: Host Statistics
By selecting Option 7 in the UART menu, packet transmission and reception statistics from the MAC can be viewed directly in the terminal validating the interoperability and reliable performance of the UDP/IP core in real-world scenarios.
Figure 5 : UDP/IP Statistics
Demo Setup 2: Board-to-Board
Overview
In this configuration, two FPGA boards are connected back-to-back over a 100G QSFP28 optical link:
- Board 1 is configured as a UDP transmitter, sending high-speed data streams.
- Board 2 is configured as a UDP receiver, validating data integrity and counting received packets.
This setup demonstrates point-to-point, deterministic, low-latency communication between two FPGA devices
Figure 6 : Board to Board Setup
Board Initialization: Both FPGA boards are powered on and their respective bitstreams are loaded. Link status is verified by reading the RX Status register on each board, confirming that the link is UP.
Configuration: Using the AXI4-Lite interface, users can access the IP registers to configure:
- Source and destination MAC addresses
- Source and destination IP addresses
- UDP port numbers
Users are prompted to select from available system configurations, after which the MAC and IP addresses are updated and displayed on screen.
Figure 7: Board Initialization
Transmission: From the main menu, Option 1 is selected to start UDP transmission. Incremental Data is chosen as the payload type to stress-test the link at full bandwidth. On the transmitter board, enabling the transmit path causes real-time packet counters to begin incrementing, confirming that data is being sent at full 100G line rate. On the receiver board, users can monitor RX packet counters, byte counters, and error indicators. The counters show zero packet loss, confirming that all transmitted frames are successfully received. The receiver’s built-in packet checker also validates payload integrity. Status registers accessible via the terminal confirm no payload errors on either system.
Figure 8: User Menu
Figure 9: Statistics
Performance Results
Across both test setups, iWave’s UDP/IP stack delivers:| Metric | Result |
| Throughput | ~96–97 Gbps |
| Packet Loss | Zero |
| Latency | 85–90 nanoseconds (deterministic) |
| CRC/FCS Errors | None |
| Dropped Packets | None |
Applications
iWave’s UDP/IP 100G IP core is well-suited for a range of high-performance networking use cases where low latency and high throughput are essential:
- High-Speed Data Acquisition & Recording: Real-time capture of massive sensor or instrumentation data, streamed to a host over 100G UDP.
- Data Center and HPC Networking: Offloading or accelerating networking workloads within servers.
- Financial and Low-Latency Trading Platforms: Sub-microsecond UDP communication for tick data and order entry.
- Real-Time Video Transport and Streaming: Continuous high-bandwidth delivery of video and audio where throughput takes priority over guaranteed delivery.
Summary
This demonstration showcased iWave’s high-performance UDP/IP 100G solution, successfully validated in both Board-to-Board and Board-to-Host configurations. The implementation delivers:
- Seamless interoperability with industry-standard NICs
- Reliable high-speed communication with zero packet loss
- Flexibility to integrate into custom user applications
iWave’s FPGA-based UDP/IP stack provides a robust, production-ready foundation for any system demanding extreme networking performance.
