August 26, 2025
Article
SmartNICs are redefining the landscape of high-performance networking by combining ultra-fast connectivity with hardware programmability to offload demanding packet processing, security, and virtualization workloads from the host CPU. In modern data centers, this translates to reduced latency, optimized server utilization, and enhanced application agility. iWave’s iW-Fibre SmartNIC platforms, powered by the DYNANIC FPGA packet processing pipeline, extend this capability through a flexible FPGA-based architecture that supports integration of new protocols, evolving security needs, and increasing performance demands, positioning them as a cornerstone of future-ready networking infrastructure.
This article explores how the DYNANIC integrates efficiently with the iW-Fibre SmartNIC platform enabling deterministic performance, modular application offloads, and low CPU utilization. Moreover, this article highlights DYNANIC application domains and presents performance metrics obtained in iW-Fibre SmartNIC.
Modern data centers encounter specific AI networking challenges: machine learning model serving platforms struggling to handle thousands of concurrent inference requests without introducing response delays; AI training clusters generating massive data synchronization traffic that saturates network links during model parameter updates; and edge AI applications requiring ultra-low latency processing where even small network delays can cause real-time decision failures in critical applications. Our partnership with DYNANIC addresses these real challenges by combining iWave’s specialized FPGA hardware with DYNANIC’s proven FPGA designs. For instance, when AI-powered applications like real-time video analytics or chatbot services receive thousands of concurrent inference requests, DYNANIC’s intelligent packet prioritization algorithms running on our FPGA platforms ensure consistent response times, preventing the network congestion that typically causes service timeouts and poor user experience.
iWave’s FPGA accelerator cards provide the hardware foundation needed for these demanding AI networking scenarios. Our platforms deliver the memory bandwidth and processing power required to handle bursts of AI inference traffic while maintaining predictable network performance. In cloud environments where AI services must respond to unpredictable user demand patterns, our hardware maintains steady packet processing rates even when inference workloads create irregular network traffic flows.
This partnership solves real AI networking problems that organizations encounter daily. When AI applications experience traffic surges during peak usage periods, causing delays in AI response times. Our joint SmartNIC solution prevents these issues by offloading network processing from the server CPU, allowing AI applications to maintain consistent performance. Organizations using our SmartNIC platform experience faster AI response times and more stable service performance, eliminating the network bottlenecks that previously constrained their AI deployments.
DYNANIC Architecture
DYNANIC provides a ready-to-use solution for offloading high-speed network traffic processing into FPGA accelerator cards, delivering all necessary software and FPGA firmware components to enable advanced SmartNIC functionality.
The architecture comprises a standardized FPGA framework that abstracts underlying hardware complexity, including pre-verified IP cores for packet parsing, filtering, memory management, and PCIe interfacing.
As shown above, ingress traffic enters through high-speed Ethernet MAC interfaces, passes through a packet parser, and is processed by multiple programmable and software-configurable (i.e., via DPDK’s rte_flow interface) filter stages supporting TCAM, LPM, exact match, and connection tracking supporting flow-based operations.
High-speed DDR4 memory provides low-latency lookups, while an edit/forward stage applies modifications before ultra-fast DMA transfers the data to or from the host via PCIe Gen3/Gen4. This design enables rapid application development without requiring deep FPGA expertise.
DYNANIC works with industry-standard software stacks including DPDK, providing direct user-space access to hardware-accelerated networking functions while maintaining compatibility with existing applications.
The DYNANIC provides a standardized FPGA framework with the core packet I/O components essential for SmartNIC operations. It features:
Integration on iW-Fibre
On the iW-Fibre platform,The DYNANIC is provided within the FPGA bitstream, enabling immediate operation with standard networking tools and DPDK applications. The architecture supports:
The result is a robust baseline for building high-throughput, low-latency network functions that can run either fully in hardware or in combination with software processing on the host.The platform delivered high throughput while maintaining low system resource consumption.
The results below highlights performance efficiency across test scenarios,
Throughput was evaluated on G35-XFibre-100G using two setups:
External Loopback
Board to Board
The performance evaluation was carried out on a Dell PowerEdge R760 server with an Intel® Xeon® Gold 6542Y CPU, 512 GB DDR5 @ 5200 MHz, and an iW-Fibre SmartNIC running the DYNANIC on Rocky Linux 9.5 (kernel 5.14) with DPDK. During the test, CPU usage remained very low for both transmit and receive operations, confirming the efficiency of DMA transfers and packet handling.
The SmartNIC consistently reached line-rate performance for standard Ethernet MTUs, demonstrating its ability to sustain full throughput in real board-to-board configurations. In both external loopback and board-to-board throughput tests, the SmartNIC delivered line-rate operation while consuming only 0.1% CPU and 3.3% memory on the host.
For throughput details on other iW-Fibre SmartNICs, contact iWave.
The iW-Fibre SmartNIC with DYNANIC supports a variety of networking and security applications, all of which were validated under actual traffic loads.
The iW-Fibre SmartNIC, powered by the DYNANIC, demonstrates how FPGA-based acceleration can deliver high throughput with minimal host resource usage. Its flexible architecture supports a wide range of networking, security, and monitoring applications, ensuring long-term relevance in evolving environments. Performance validation through loopback and board-to-board testing confirms the platform’s ability to sustain line-rate operation efficiently. By offloading complex packet processing from the CPU, the SmartNIC enhances server utilization and reduces latency. This combination of performance, efficiency, and adaptability positions the solution as a strong enabler for next-generation data center and security-driven deployments.
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