Programming Protocol-independent Packet Processors (P4) is a programmable language that enables developers to define how packets are processed in the network data plane, offering flexibility beyond fixed-function hardware. Using P4, iW-Fibre SmartNICs can perform key offloads such as packet forwarding and IP checksum verification, both executed at line rate for maximum performance.
Checksum verification and Packet Forwarding
As network traffic continues to grow and applications demand ultra-low latency and high throughput, traditional CPU-based packet processing can no longer keep pace. Tasks such as packet forwarding and checksum verification, when performed in software, consume significant CPU cycles, and limit overall performance. P4-enabled SmartNICs address these challenges by offloading these operations to programmable hardware, where custom P4 logic implemented using the Altera P4 Suite, runs at line rate. This enables:
- IP Checksum Verification: Ensures packet header integrity by validating checksum values directly in hardware.
- Packet forwarding: Determines the next-hop destination of packets based on lookup tables.
By executing these functions directly in the data plane, SmartNICs deliver higher throughput, and reduced CPU utilization while maintaining flexibility and scalability.
Why we need these offloads
CPU bottleneck: As network speeds increase to 100 Gbps and beyond, the CPU is quickly overwhelmed by the sheer volume of packets that need processing. This makes the host CPU a bottleneck that limits the network’s overall throughput.
Resource efficiency: Offloading packet processing to a P4 SmartNIC frees up the host CPU to focus on revenue generating/higher priority tasks. This is especially crucial in virtualized and cloud-native environments where CPU cycles are a precious resource for multi-tenant workloads
Packet-processing burden: With millions of packets per second, the host CPU spends a disproportionate number of cycles on basic, repetitive tasks like checksum validation. In many data flows, checksums may need to be computed multiple times at different stages, further increasing the processing overhead. Offloading this task to the SmartNIC’s specialized hardware or FPGA not only reduces this repetitive workload but also frees the host CPU to focus on application logic, thereby improving overall system performance.
Packet forwarding and Checksum Verification Architecture
- Data plane:
The iW-Fibre card receives IPv4 packets from either the network or the host and processes them through the P4 pipeline. The image below depicts the packet processing flow carried out by the Match-Action engine.
Checksum Verification
- Inside the P4 pipeline, the IPv4 headers are parsed, and the IP checksum is calculated using the built-in P4 extern “Internet Checksum”.
- The Internet Checksum P4 extern computes the IPv4 header checksum by processing all IP header fields except the checksum field itself. It uses the One’s Complement Checksum method, which inherently accounts for differences between big-endian and little-endian CPU architectures during computation.
- The calculated checksum is then compared with the actual checksum field that comes with the packet header. If the values do not match, the packet will be dropped.
- If the values match, the packet proceeds to the next function.
Packet Forwarding
- Once the Checksum verification is done, the Match-Action module compares the Ethernet destination address of the packet against keys in the lookup table (LUT).
- If a match is found, the packet is forwarded to the output port specified in the corresponding LUT entries; otherwise, it can be handled according to the default action (e.g., forwarding to default port).
2. Control plane:
The Control Plane defines how packets are processed and forwarded within the network.
The user provides the P4 LUT (Lookup Table) entries such as the Ethernet destination address and the egress port (next hop) through the Control Plane software application, allowing dynamic manipulation of packet forwarding routes without requiring any hardware updates. The previous image illustrates how the user accesses the LUT (Lookup Table) for P4 offload operations.
For more information on Control Plane refer to the Article “Building a P4-Programmable SmartNICs through iW-Fibre cards: Architecture and Insights”.
In summary, integrating P4 with iW-Fibre SmartNICs enables a fully programmable and efficient data plane, allowing network functions to be customized, accelerated, and executed at line rate significantly enhancing performance, scalability, and adaptability in modern network infrastructures.
