High-speed chip-to-chip communication is a critical requirement in modern data-intensive systems such as 5G infrastructure, AI-driven networking platforms, and high-frequency trading environments. 150G Interlaken is a widely adopted for high-speed serial interface protocol designed to meet these requirements by enabling low-latency, scalable data transfer between devices. As an open-standard serial interface, 150G Interlaken supports flexible lane configurations along with strong error-handling mechanisms, making it well suited for high-bandwidth applications.
iWave’s Zynq™ UltraScale+™ MPSoC platforms, powered by AMD support soft 150G Interlaken implementations, enabling throughput of up to 150 Gbps per block using 6 lanes operating at 25.78125 Gbps. This capability allows designers to implement efficient, high-performance interconnects for next-generation networking and compute platforms.
The 150G Interlaken IP core is offered under the AMD Project License. Once the Project License Agreement is executed, the IP core functionality is enabled based on the selected device part number. The core interfaces with Gigabit Transceivers (GTs) for high-speed serial I/O and provides a flexible protocol layer that reduces pin count and power consumption. Its burst-oriented transfer mechanism makes it especially suitable for packet-based processing and network acceleration use cases.
Architecture
The Interlaken 150G IP core is delivered as a soft macro, allowing straightforward implementation on supported AMD devices. It is commonly used as a chip-to-chip interconnect between multiple system components, taking advantage of Interlaken’s ability to operate across a range of lane widths and line rates to match specific bandwidth requirements.
The lane-logic-only mode enables each serial transceiver to participate in forming a complete Interlaken interface. To deploy the core, it must be connected to the high-speed serial transceiver blocks, supplied with the required clock sources, and interfaced to the Local Bus (LBUS) on the user side. This architecture simplifies integration while maintaining high performance and scalability.
Applications
- Data Center and Telecom Infrastructure: Enables scalable line card to switch fabric connectivity in routers and switches.
- Framer/MAC to Network Components: Provides efficient interfaces between Framer/MAC blocks and switch fabrics, NPUs, or traffic managers for high-speed packet handling.
- High-Speed Backplane and Memory Interfaces: Supports TCAM and buffer memory connectivity, as well as reliable high-speed backplane links in enterprise systems.
- Enterprise and Cloud Computing: Delivers low-latency, high-throughput interconnects for cloud servers and enterprise networks, supporting AI, big data, and virtualized workloads.
- Networking Applications: Used in channelized, high-bandwidth systems such as routers, switches, optical transport equipment, 5G base stations, and edge-computing platforms.
iG-G35D: Zynq™ UltraScale+™ ZU19EG MPSoC Dev Kit
- The iWave ZU19EG-2 development kit uses 6 GTY transceiver lanes operating at 25.78125 Gbps per lane to achieve an bandwidth of 150 Gbps.
- The ZU19EG-2 development kit uses Quad QSFP28/QSFP+ FMC+ module that supports 4 QSFP28/QSFP+ ports with a total of 16 high-speed transceivers.
- 6 High speed transceivers from banks 129 (X0Y8–X0Y11) and 130 (X0Y12–X0Y13) are configured to operate with the 150G Interlaken IP core.
- 195.3125 MHz GT reference clock is used from the on-board Clock Synthesizer-2, with clock synthesizer configurations handled within the FSBL.
- The development kits are interconnected using Quad QSFP28/QSFP+ FMC+ modules and two QSFP board-to-board connectors. The top stacked connector (bank 129) and bottom stacked connector (bank 130) are used to link the two boards through four QSFP28/QSFP+ interfaces.
Interlaken IP Integration
The following sequence outlines the operation after the 150G Interlaken IP core is powered up:
- After the device is powered up and the reset procedure completed, the Interlaken 150G IP core TX path starts transmitting Control/Idle words to align and synchronize the receiving device Interlaken interface. Similarly, the core RX path receives Control/Idle words and completes its own synchronization procedure.
- Set all of the flow control inputs to the Interlaken 150G IP core TX path to the XOFF state to prevent any real data transfer.
- The RX path is eventually aligned and synchronized and signals the user logic that synchronization is complete. You can then turn the flow control information from XOFF to XON for any of the channels that are ready to accept data.
- When the other device is ready to receive data, it sends XON information to the Interlaken 150G IP core. The core will signal the user logic which channels can be used for data transmission.
Why 150G Interlaken Is Required
- Efficiency: High-speed serial interfaces such as 150G Interlaken significantly reduce pin count, lower power consumption, and offer improved immunity to electromagnetic interference compared to parallel interfaces.
- Reliability: The protocol enables reliable chip-to-chip data transfer without dependence on higher-layer communication protocols.
- Scalability, Configurability, and Reuse: Interlaken interfaces can be scaled and reconfigured to support varying data rates, allowing reuse across multiple system designs and applications.
Conclusion
The validation of 150G Interlaken on the Zynq™ UltraScale+™ ZU19EG MPSoC platform demonstrates a robust and high-performance solution for next-generation chip-to-chip interconnects. By integrating iWave’s ZU19EG Zynq UltraScale+ SoM with AMD technology, this platform enables efficient data acquisition and processing, making it well suited for demanding high-speed communication and networking applications.
For more information or inquiries, reach out to mktg@iwave-global.com
