Frequency Modulated Continuous Wave (FMCW) radar is widely used for range and velocity measurement because it can continuously transmit a frequency swept waveform while simultaneously receiving the reflected signal from a target. By comparing the transmitted chirp with the received echo, the radar determines the beat frequency, which contains information about the target’s distance and motion.
An RFSoC based platform is particularly well suited for FMCW radar implementation because it integrates high speed ADCs, DACs, programmable FPGA logic, memory, and processing resources into a single device. This enables the complete digital radar signal-processing chain from waveform generation and data acquisition to digital mixing and filtering to be implemented on the RFSoC.
The setup shown in the snapshot demonstrates an FMCW radar proof of concept using an RFSoC development kit, with an RF loopback path used in place of an over the air antenna and target.
How FMCW Radar Works?
- An FMCW radar transmits a continuous signal whose frequency changes with time. The transmitted signal travels toward the target and is reflected back to the receiver after a propagation delay.
- The transmitted signal travels toward the target and is reflected back to the receiver after a propagation delay.
- The received signal therefore represents a delayed version of the transmitted chirp. When the received chirp is mixed with a copy of the transmitted chirp, a lower-frequency beat signal is generated.
- This is the fundamental principle used by the FMCW radar
How RFSoC-Based FMCW Radar Architecture Looks like?
The implementation shown in the snapshot can be divided into following major sections:
- FMCW chirp generation: The RFSoC DAC can be configured to generate the desired chirp waveform digitally. The chirp can be generated using an FPGA-based numerically controlled oscillator (NCO), DDS, lookup table, or an RFSoC waveform generation framework.
- RF transmission and loopback: In the setup shown in the snapshot, the DAC output is connected to an RF divider. One branch can be used as the transmit/reference signal, while another branch is routed through the loopback path. The attenuator is important because it reduces the signal level before it reaches the ADC and can emulate the attenuation associated with a radar propagation path.
- High-speed ADC acquisition: The RFSoC ADCs simultaneously digitize the reference and received signals. The two ADC channels can be considered,
- ADC 1: transmitted/reference chirp
- ADC 2: received/echo chirp
The RFSoC’s integrated high speed ADCs allow the radar receiver to directly sample the RF/IF signal, depending on the selected RF frequency and system architecture.
- Digital beat-frequency processing: The most important signal processing operation is the comparison between the transmitted and received chirps. The FPGA can perform this operation using a complex multiplier. This operation removes the high frequency carrier component and produces a lower-frequency beat signal. The mixer output may contain unwanted high-frequency components and noise and a digital low-pass filter can therefore be applied after the mixer.This is one of the major advantages of using the FPGA fabric: the high speed mixing operation can be performed continuously and in parallel.
- Host PC processing and visualization: The filtered mixer output is then transferred to the host PC for further radar signal processing. Using GNU Radio or a custom host application, the beat-frequency data can be processed through FFT and range/Doppler algorithms to extract key target parameters such as range and radial velocity. With appropriate multi-channel antenna and phase-processing techniques, the system can also estimate the target’s azimuth and elevation angles.
From Loopback Demonstration to Real Radar
The setup shown above is primarily a radar signal processing validation platform. The loopback cable substitutes for the propagation path and target. For a real FMCW radar, the loopback section can be replaced with RF Front End, Power Amplifier and Antenna.
Depending on the operating frequency, the system may require additional RF components such as:
- PA
- LNA
- filters
- mixers
- LO/synthesizer
- T/R switch or circulator
- antenna array
- calibration circuitry
The RFSoC then acts as the digital radar processing and waveform-generation platform.
Why RFSoC is Suitable for FMCW Radar?
An RFSoC-based implementation provides several benefits for FMCW radar development.
The architecture also allows the same hardware platform to be adapted for different radar modes and bandwidth requirements.
Conclusion
The RFSoC development kit setup described above provides a practical starting point for implementing an FMCW radar entirely around a programmable RFSoC platform. The DAC generates the FMCW chirp, the RF path provides the transmit/echo signals, and the integrated ADCs digitize the received and reference signals. The FPGA fabric can then perform complex mixing, filtering, decimation and GNU radio can take care of the FFT processing, and range/Doppler extraction in real time.
The loopback configuration is particularly useful for initial validation because it allows the complete digital radar chain to be tested without requiring an antenna, RF power amplifier, or physical target. Once the waveform generation, beat-frequency extraction, range calculation, and Doppler processing are validated, the same architecture can be extended to an over-the-air radar by adding the appropriate RF front end and antenna subsystem.
In an iWave oriented implementation, this can form the basis of an RFSoC FMCW Radar platform combining RFSoC hardware, FPGA based radar DSP, PCIe/Ethernet connectivity, and a GNU Radio or custom host application.
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