ULL Fintech Accelerations

• Tick-to-trade latency of < 300 ns
• Complete trading path implemented in FPGA fabric, with no host CPU or PCIe crossing between market-data ingress and order egress
• Single-clock-domain, fully pipelined trading datapath
• Deterministic processing for predictable trading response

Network Interface

• 10GBASE-R low-latency MAC/PCS implemented on GTY transceivers
• Direct 32-bit PMA interface with transceiver buffer bypass for reduced datapath latency
• Ultra-low-latency UDP/IP TX/RX stack optimized for market-data reception and packet processing
• TCP/IP interface optimized for low-latency order placement and exchange communication

Market Data & Order Book

• NASDAQ ITCH 5.0 market-data parser
• Symbol filtering at ingress
• Per-symbol, price-level order-book reconstruction in FPGA fabric
• Incremental Best Bid and Offer (BBO) updates without full book rescanning

Trading Strategy & Order Entry

• User-programmable strategy region with AXI4-Stream market-event input and order-request output
• Reference market-making and fair-value pricing strategies
• NASDAQ OUCH 5.0 order encoder
• SoupBinTCP session layer with hardware TCP offload
• Parallel CRC32 processing across the datapath

• Linux host driver and API for configuration and framework management
• Symbol subscription, risk-limit and strategy-parameter configuration
• Telemetry for link status, order and risk-rejection counters
• PCIe DMA for market-data and order-log drop copy

• 3/4 Length PCIe Gen3 x16 Host Interface
• Dual Front Panel QSFP-DD/QSFP28 Cages (3 x 10GbE) via breakthrough cables
• 254mm x 111.15mm, 3/4 Length, Full Height, Dual Slot with Active Cooling PCIe Card
• Quad/Dual Arm Cortex-A53 @1.5GHz, Dual Cortex-R5 @600MHz
• Up to 1143K Logic cells & 522K LUTs in FPGA programming logic
• Product Info: Zynq™ Ultrascale+™ SmartNIC – 100G

• PCIe Gen5 x8 Host Interface
• QSFP-DD Connector x 3 (3 x 10GbE) via breakthrough cables
• Full height, ¾ Length, Single Slot with Active Cooling PCIe Card
• Dual-core Arm Cortex-A72 @1.7GHz, Dual-core Arm Cortex-R5F @800MHz
• Up to 3763K Logic cells and 1720K LUTs in FPGA programming logic
• Product Info: Versal™ Premium SmartNIC – 400G

• PCIe Gen5 x16 Host Interface
• 3/4 Length, Full Height, Single Slot with Active Cooling PCIe Card.
• Quad Core ARM Cortex A53
• upto 2.7M Logic elements
• Product Info: Agilex™ 7 I-Series R and F Tiles SmartNIC – 400G

• PCIe Gen4 x 4 Host Interface
• Half length Form factor PCIe Gen4 x4 NIC card
• Dual core 64-bit ARM Cortex-A76 up to 1.8 GHz, Dual core
• 64-bit ARM Cortex-A55 up to 1.5 GHz
• upto 656K Logic elements
• Product Info: Agilex 5 SmartNIC Network and Storage Accelerator Card