Next-generation Electronic Warfare (EW) platforms must simultaneously detect, analyze, classify, and counter complex RF threats across wide frequency ranges and under stringent latency constraints. Traditional architectures using discrete RF converters, FPGAs, and processors increase system complexity, power consumption, and response time.
This case study demonstrates how an iWave’s RFSoC-based System on Module architecture enables a unified, multi-role EW platform, capable of supporting Radar Warning Receiver (RWR), DRFM Jammer, and SIGINT/ELINT Receiver functions on a single, scalable hardware platform.
System Architecture Overview
The system is built around an Zynq UltraScale+ RFSoC device integrating high-speed ADCs, DACs, FPGA fabric, and Arm processing cores. Wideband RF signals from the antenna are conditioned by the RF front end and directly digitized by the on-chip ADCs, eliminating external data converter latency and interconnect bottlenecks.
Real-time signal processing is partitioned across:
- FPGA fabric for deterministic, low-latency DSP operations
- Integrated DSP blocks for high-throughput math-intensive functions
- Arm processing subsystem for control, classification, and higher-level decision logic
High-speed memory and I/O interfaces enable buffering, storage, and data offload for further analysis.
Electronic Warfare Functional Capabilities
Radar Warning Receiver (RWR)
The RWR mode focuses on early detection and characterization of hostile radar emissions.
- Wideband RF capture using high-speed RFSoC ADCs
- FPGA-based channelization, pulse detection, and time-frequency analysis
- Extraction of key radar parameters such as PRI, pulse width, frequency, and amplitude
- Threat classification algorithms running on Arm cores using predefined or adaptive libraries
- Real-time generation of threat alerts and countermeasure trigger signals
This tightly coupled processing chain enables fast reaction times critical for survivability.
DRFM Jammer Function
In DRFM mode, the system performs deceptive jamming by capturing, modifying, and retransmitting hostile radar signals with minimal latency.
- Wideband I/Q sampling of incoming radar signals
- High-speed DDR memory used as a circular buffer for real-time signal storage
- FPGA-based signal manipulation including:
- Programmable delay insertion
- Doppler shift generation
- Amplitude and phase modification
- Re-transmission through integrated RFSoC DACs
- Sub-microsecond capture-to-output latency enabled by on-chip ADC/DAC and FPGA fabric
The close integration of converters and processing logic allows high-fidelity, low-latency jamming without external data movement.
SIGINT / ELINT Receiver Function
The SIGINT/ELINT mode supports wideband surveillance, interception, and signal intelligence.
- Full Nyquist-rate RF capture across wide frequency spans
- FPGA-based DDC channelization using polyphase filter banks
- Parallel demodulation chains for AM, FM, PSK, FSK, and other modulation types
- Arm-based modulation classification and signal parameter extraction
- On-board storage to NVMe SSDs or high-speed streaming over Ethernet to external processing systems
This architecture supports simultaneous monitoring and analysis of multiple emitters in dense RF environments.
Key System Advantages
- Ultra-low latency architecture through integrated ADC, DAC, and FPGA fabric
- Wideband, multi-channel RF capability supporting concurrent EW functions
- Software-defined and reconfigurable processing, enabling rapid mission updates
- Reduced SWaP compared to discrete RF + FPGA solutions
- Scalable design suitable for PCIe cards or rugged 3U VPX SOSA-aligned platforms
This multi-role RFSoC-based EW architecture highlights how a single, flexible platform can be adapted to perform RWR, DRFM jamming, and SIGINT/ELINT roles, reducing system complexity while increasing operational agility. This demonstrates readiness for future EW missions requiring fast response, wideband coverage, and continuous adaptability.
For more information, please write to us at mktg@iwave-global.com
